@article{article, title  = {{Fast parallel-prefix architectures for modulo 2(n)-1 addition with a single representation of zero}},

 url = {{}},

 year = {{2007}},

 month = {{11}},

 author = {{Patel RA and Benaissa M and Boussakta S}},

 doi = {{10.1109/TC.2007.70750}},

 volume = {{56}},

 journal = {{IEEE T COMPUT}},

 issue = {{11}},

 pages = {{1484-1492}},

 note = {{Accessed on 2024/12/22}}}