TY  - JOUR

T1  - Reconfigurable hardware architectures for sequential and hybrid decoding

JO  - IEEE T CIRCUITS-I

PY  - 2007/03/01

AU  - Benaissa M

AU  - Zhu YQ

ED  - 

DO  - DOI: 10.1109/TCSI.2006.887600

VL  - 54

IS  - 3

SP  - 555

EP  - 565

Y2  - 2024/12/22

ER  -